As integrated circuits have become more complex employing more and more pins in a limited area, and more input/output (I/O) signal pins are switching at high speed at the same time, decoupling the power supplies through efficient usage of low inductance capacitors is essential. Current techniques for incorporating decoupling capacitors include: i) placing discrete capacitors coplanar to the integrated circuit (IC) die on the top surface of the substrate; and ii) placing discrete capacitors onto the underside of the package, coplanar to the BGA balls.
The first approach, of placing discrete capacitors coplanar to the IC die, is cost effective, but suffers from the following drawbacks: a) the effective inductance of the decoupling network ranges around 400 pH to 600 pH, due to the cumulative effect of the horizontal/lateral spreading inductance of the power plane between the power bump locations in the IC die and the capacitor location, the inductance contributed by the vias, and the ESL (Equivalent Series Inductance) of the capacitor; b) the placement of capacitors and the feasible quantity of capacitors are very constrained, due to die-to-capacitor keep-out and capacitor to package-edge keepout rules; c) the capacitors interfere with signal routing as the mounting pads for the capacitors act as obstacles to the routing paths; d) capacitors obstruct the placement and attachment of the lid by limiting the amount of area available for the lid to contact the substrate, potentially causing lid separation in field usage due to poor adhesion; and e) in some IC die and package size combination, there is not enough real estate for placing any capacitors.
The second approach, of placing discrete capacitors onto the under side of the package, either vertically direct below the IC die bump location or nearby, allows for reasonably low inductance decoupling at around 100 pH by careful design, exhibits certain deficiencies: a) for each capacitor that is placed, two or more pin locations of the package need to be depopulated (that is, removed from communicating between the package and the PCB); b) the power bump locations on the die dictate where the capacitor and pin depopulation should be, which renders pinout sharing among differently sized dice impractical; and c) in applications where a high number of capacitors or other useful passive and/or active components are required, the pin depopulation constricts the available number of pins available for a designated package size. This could also limit the pinout pattern design and prevent implementation of a high performance pinout pattern.
Accordingly, there is a need for a flip chip package with integrated capacitors that is low-inductance capable, with high capacity in both unit count and capacitance, with design flexibility, constraint-free pinout, allowing multiple passive or active component types.